1. Field of the Invention
The present invention relates to packaging semiconductor chips, and more particularly to a wafer level chip scale package (WLCSP) having continuous through hole vias (THVs) and a fabrication method thereof.
2. Description of the Prior Art
A wafer level chip scale package (WLCSP) is different from a conventional semiconductor package. The integrated circuits of the WLCSP are tested and packaged in the wafer stage before dicing the WLCSP. The size of the WLCSP is not greater than 1.44 times of the size of the chips. A WLCSP usually has double-sided longitudinal electrical interconnections for connecting terminals to the bottom of the chip to reduce the size of the substrate or omit the substrate. A conventional double-sided longitudinal electrical interconnection may be a through hole via (THV) or a chip side redistribution layer (RDL).
In the packaging process of a conventional WLCSP using through hole vias (THVs), a plurality of composite stacked chips are packaged in the wafer stage. Each of the composite stacked chips has a device chip and a carrier chip integrated with the device chip. A laser drill or an etching process may be performed to form through holes penetrating through the device chip and the carrier chip. The through holes may be filled with copper (Cu), an alloy of gold (Au), nickel (Ni) and copper (Cu), polysilicon, tungsten (Wu) or other conductive materials to form the double-sided longitudinal electrical interconnections of the composite stacked chip. Since the chips could be electrically connected to the substrate without performing a wire bonding process, the area of the substrate may be used more effectively and the packaging process can be simplified. However, it is difficult to control the depth of the through holes when performing the laser drill or the etching process, causing over-etching or under-etching of the through holes. When the through holes are over-etched, the through holes may penetrate through the solder pads of the device chip, diffusing the etching material or etching plasma to an active area of the device chip, polluting the electronic elements, and resulting in interconnection failure between solder pads and the conductive material filled in the through holes. When the through holes are under-etched, the conductive material filled in the through holes would fail to connect to the solder pads.